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xicor, inc. 1994, 1995, 1996 patents pending 7052 10/29/00 t0/c0/d2 sh 1 characteristics subject to change without notice 128k x76f128 1 6kx8+64x8 functional diagram secure features ?64 - bit password security ?five 64-bit passwords for read, program and reset ?16384 byte+64 byte password protected arrays ? seperate read passwords ?seperate write passwords ? reset password ?programmable passwords ?retry counter register ? allows 8 tries before clearing of both arrays ?password protected reset ?32 - bit response to reset (rst input) ?64 byte sector program ?400khz clock rate ?2 wire serial interface ?low power cmos ? 2.7 to 5.5v operation ?standby current less than 1a ?active current less than 3 ma ?high reliability endurance: ?100,000 write cycles ?data retention: 100 years ?available in: ? smartcard module ?tqfp package description the x76f128 is a password access security superviso r, containing one 131072-bit secure serialflash array and one 512-bit secure serialflash array. access to each memory array is controlled by two 64-bit pas swords. these passwords protect read and write operat ions of the memory array. a separate reset password is used to reset the passwords and clear the memory arrays in the event the read and write passwords are lost. the x76f128 features a serial interface and software protocol allowing operation on a popular two wire bus. the bus signals are a clock input (scl) and a bidir ec- tional data input and output (sda). access to the d evice is controlled through a chip select (cs) inp ut, allowing any number of devices to share the same bus. the x76f128 also features a synchrono us response to reset providing an automatic output of a hard-wired 32-bi t data stream conforming to the industry standa rd for memory cards. the x76f128 utilizes xicor?s proprietary direct wri te tm cell, providing a minimum endurance of 100,000 cycl es and a minimum data retention of 100 years. logic cs scl sda rst interface 16k byte data transfer array access enable reset response register password array and password verification logic chip enable retry counter serialflash array 64 byte serialflash array array 0 array 1 (password protected) (password protected) 7052 fm 01 this x76f128 device has been acquired by ic microsystems from xicor; inc.
x76f128 2 pin descriptions serial clock (scl) the scl input is used to clock all data into and ou t of the device. serial data (sda) sda is a true three state serial data input/output pin. dur- ing a read cycle, data is shifted out on this pin. duri ng a write cycle, data is shifted in on this pin. in all other cases, this pin is in a high impedance state. chip enable (cs) when cs is high, the x76f128 is deselected and the sda pin is at high impedance and unless an internal write operation is underway, the x76f128 will be in standby mode. cs low enables the x76f128, placing i t in the active mode. reset (rst) rst is a device reset pin. when rst is pul sed high while cs is low the x76f128 will output 32 bits of fixed data which conforms to the standard for ?syn chronous response to reset?. cs must remain low and the part must not be in a write cycle for the response to re set to occur. see figure 11. if at any time during the res ponse to reset cs goes high, the response to rese t will be aborted and the part will return to the standby sta te. the response to reset is "mask programmable" only! device operation there are two primary modes of operatio n for the x76f128; protected read and protected write. protected operations must be performed with one of four 8- byte passwords. the basic method of communication for the de vice is established by first enabling the device (cs low), gen- erating a start condition, then transmitting a comm and, followed by the correct password. all p arts will be shipped from the factory with all passwords equal t o ?0?. the user must perform ack polling to determine t he validity of the password, before starting a data transfer (see acknowledge polling.) only after the correct p ass- word is accepted and a ack polling has been perform ed, can the data transfer occur. to ensure the correct communication, rst must remai n low under all conditions except when ru nning a ?response to reset sequence?. data is transferred in 8- bit segments, with each transfer being followed by an ack, generated by the receivi ng device. if the x76f128 is in a nonvolatile write cycle a ?n o ack? (sda=high) response will be issued in response to l oad- ing of the command byte. if a stop is issued prior to the nonvolatile write cycle the write operation will be termi- nated and the part will reset and enter int o a standby mode. the basic sequence is illustrated in figure 1. pin names pin configuration after each transa ction is completed, the x76f128 will reset and enter into a standby mode. this will also be the response if an unsuccessful attempt is made to acce ss a protected array. symbol description cs chip select input sda serial data input/output scl serial clock input rst reset input vcc supply voltage vss ground nc no connect v cc rst scl nc sda smart card cs nc 7052 fm 02 gnd 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 vcc nc nc nc nc nc nc nc nc nc rst scl vss nc nc nc nc nc nc nc nc nc cs sda 7052 fm t01 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc n c
x76f128 3 figure 1. x76f128 device operation retry counter the x76f128 contains a retry counter. the retry cou nter allows 8 accesses with an invalid password before a ny action is taken. the counter will increment with an y com- bination of incorrect passwords. if the retry count er over- flows, all memory areas are cleared and the device is locked by preventing any read or write array password matches. the passwords are unaffected. if a correct password is received prior to retry counter overflo w, the retry counter is reset and access is granted. in or der to reset the operation of a locked up device, a specia l reset command must be used with a reset password. device protocol the x76f128 supports a bidirectional bus oriented p ro- tocol. the protocol defines any device that sends d ata onto the bus as a transmitter and the receiving dev ice as a receiver. the device controlling the transfer is a master and the device being controlled is the slave. the m aster will always initiate data transfers and provide the cloc k for both transmit and receive operations. therefor e, the x76f128 will be considered a slave in all applicati ons. clock and data conventions data states on the sda line can change only during scl low. sda changes during scl high are reserved for indicating start and stop conditions. refer to figu re 2 and figure 3. start condition all commands are preceeded by the start cond ition, which is a high to low transition of sda when scl i s high. the x76f128 continuously monitors the sda and scl lines for the start condition and will not resp ond to any command until this condition is met. a start may be issued to terminate the input of a c ontrol byte or the input data to be written. this will reset the device and leave it ready to begin a new read or wr ite command. because of the push/pull output, a start c an- not be generated while the part is outputting data. starts are inhibited while a write is in progress. stop condition all communications must be terminated by a stop con di- tion. the stop condition is a low to high transitio n of sda when scl is high. the stop condition is also us ed to reset the device during a command or data i nput sequence and will leave the device in the standby p ower mode. as with starts, stops are inhibited when outp utting data and while a write is in progress. acknowledge acknowledge is a software convention used to indica te successful data transfer. the transmitting devi ce, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it receiv ed the eight bits of data. the x76f128 will respond with an acknowledge after recognition of a start condition and its slave addr ess. if both the device and a write condition have been selected, the x76f128 will respond with an acknowle dge after the receipt of each subsequent eight-bit word . reset device command the reset device command is used to clear the retry counter and reactivate the device. when the reset device command is used prior to the retry c ounter overflow, the retry counter is reset and no arrays or pass- words are affected. if the retry counter has overfl owed, all memory areas are cleared and all comman ds are blocked and the retry counter is disabled. issuing a valid reset device command (with reset password) to the device resets and re-enables the retry counte r and re- enables the other commands. again, the passwords ar e not affected. reset password command a reset password command will clear both arrays and set all passwords to all zero. load command byte load 2 byte address load 8-byte password verify password acceptance by use of password ack polling read/write data bytes 7052 fm 03 twc or data ack polling
x76f128 4 figure 2. data validity figure 3. definition of start and stop conditions table 1. x76f128 instruction set notes: illegal command codes will be disregarded. the part wi ll respond with a ?no-ack? to the illegal byte and t hen return to the standby mode. all write/read operations require a password. 1st byte after start 1st byte after password 2nd byte after pas sword command description password used 1000 0000 high address low address read (array 0) r ead 0 1000 1000 high address low address read (array 1) r ead 1 1001 0000 high address low address sector write (ar ray 0) write 0 1001 1000 high address low address sector write (ar ray 1) write 1 1010 0000 0000 0000 0000 0000 change read 0 passwor d read 0 1010 1000 0000 0000 0000 0000 change read 1 passwor d read 1 1011 0000 0000 0000 0000 0000 change write 0 passwo rd write 0 1011 1000 0000 0000 0000 0000 change write 1 passwo rd write 1 1100 0000 0000 0000 0000 0000 change reset password reset 1110 0000 not used not used reset password command reset 1110 1000 not used not used reset device command reset 1111 0000 not used not used ack polling command (ends password oper ation) none all the rest reserved scl sda data stable data change 7052 fm 04 scl sda start condition stop condition 7052 fm 05 7052 fm t04
x76f128 5 program operations sector programming the sector program mode requires issuing the 8-bit write command followed by the password, password ack com- mand, the address and then the data bytes transferr ed as illustrated in figure 4. up to 64 bytes may be tran s- ferred. after the last byte to be transferre d is acknowl- edged a stop condition is issued which starts the nonvolatile write cycle. figure 4. sector programming data 63 s command write password 7 write password 0 data 0 s sda wait t wc data ack polling . . . wait t wc or ack polling s ack polling repeated command command if ack, then password matches 7052 fm 07 ack ack start ack ack ack ack ack ack a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ack stop ack nack start
x76f128 6 ack polling once a stop condition is issued to indicate the end of the host?s write sequence, the x76f128 initiates the in ternal nonvolatile write cycle. in order to take advantage of the typical 5ms write cycle, ack polling can begin immediately. this involves issuing the sta rt condition followed by the new command code of 8 bits (1st byt e of the protocol.) if the x76f128 is still busy with the nonvolatile write operation, it will issue a ?no-ack? in response. if the nonvolatile write operation has completed, an ?ack? will be returned and the host can then proceed with the rest of the protocol. after the password sequence, there is always a nonv ola - tile write cycle. this is done to discourage random guesses of the password if the device is being tamp ered with. in order to continue the transaction, the x7 6f128 requires the master to perform an ack pollin g with the specific code of f0h. as with regular acknowledge p olling the user can either time out for 10ms, and then iss ue the ack polling once, or continuously loop as described in the flow. if the password that was inserted was correc t, then an ?ack? will be returned once the nonvolatile cycle i s over, in response to the ack polling cycle immediately fo llowing it. if the password that was inserted was incorrect, th en a ?no ack? will be returned even if the nonvolatile cycle is over. therefore, the user cannot be certain that the pass word is incorrect until the 10ms write cycle time has elaps ed. data ack polling sequence ack returned ? issue new command code write sequence completed enter ack polling issue start no yes proceed 7052 fm 08 password ack polling sequ ence ack returned ? issue password ack command password load completed enter ack polling issue start no yes proceed 7052 fm 09 figure 5. acknowledge polling 8th clk. of 8th pwd. byte ?ack? clk 8th clk ?ack? clk ?ack? start condition 8th bit ack or no ack scl sda 7052 fm 10
x76f128 7 read operations read operations are initiated in the same manner as write operations but with a different command code. random read the master issues the start condition and a read in struc- tion and password, performs a password ack polling, then issues the word address. once the password h as been acknowledged and first byte has been read, another start can be issued followed by a new 8-bit address. rand om reads are allowed, but only the low order 8 bits can change. this limits random reads to a 512 b yte block. therefore, with a single password cycle only a 512 byte block of array 0 may be accessed randomly. to rando mly access another block of array 0, a stop must be iss ued fol- lowed by a new command/address/password sequence. a random read of the array 1 can access all locations with- out another password command sequence. sequential read the host can read sequentially within an arr ay after the password acceptance sequence. the data ou tput is sequential, with the data from address n followed b y the data from n+1. the address counter for read operat ions increments all address bits, allowing the ent ire memory array contents to be serially read during one opera tion. at the end of the address space (address 3fffh for arr ay 0, 3fh for array 1), the counter ?rolls over? to addre ss 0 and the x76f128 continues to output data for each ackno wl- edge received. refer to figure 7 for the address, a cknowl- edge and data transfer sequence. an acknowledge mus t follow each 8-bit data transfer. after the last bit has been read, a stop condition is generated without a preceding acknowledge. figure 6. random read s data y s command read password 7 read password 0 s sda data x wait t wc or ack polling s ack polling repeated command command if ack, then password matches 7052 fm 11 figure 7. sequential read data x s command read password 7 read password 0 s sda data 0 if ack, then wait t wc or ack polling s ack polling repeated command command password matches 7052 fm 12 ack stop a7 a6 a5 a4 a3 a2 a1 a0 start start ack ack ack ack ack ack a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 start ack nack ack start ack ack ack ack ack ack a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ack start ack nack stop
x76f128 8 passwords the sequence in figure 8 shows how to chang e (pro- gram) the passwords. the programming of passwords i s done twice prior to the nonvolatile write cycle in order to verify that the new password is consistent. after t he eight bytes are entered in the second pass, a com parison takes place. a mismatch will cause the part to rese t and enter into the standby mode. data ack polling can be used to determine if a pass word has been loaded correctly, however the data ack com - mand must be issued less than 2ms after the stop bit. after this time, it cannot be determined if the pas sword has been loaded correctly, without trying the new p ass- word. to determine if the new password has been loa ded correctly the data ack polling command is issued im me- diately following the stop bit. if it returns an ac k, then the two passes of the new password entry do not match. if i t returns a "no ack" then the passwords match and a h igh voltage cycle is in progress. the high volta ge cycle is complete when a subsequent data ack com mand returns an "ack". there is no way to read any of the passwords. figure 8. change passwords figure 9. reset password command old password 7 old password 0 s sda new password 7 password 0 new password 7 new password 0 s if ack, then two bytes of ?0? wait t wc or ack polling s ack polling repeated command command password matches if immediate ack, then new password error data ack polling if immediate nack, then new password ok followed by ack after ~5ms 7052 fm 13 reset password reset password 7 reset password 0 s sda wait t wc or ack polling s ack polling repeated command command s if ack, then device reset command 7052 fm 14 start ack ack ack ack ack ack ack ack ack ack ack stop ack st art ack nack start ack ack ack ack start ack nack stop
x76f128 9 figure 10. reset device reset device reset password 7 reset password 0 s sda wait t wc or ack polling s ack polling repeated command command s if ack, then device reset command 7052 fm 15 absolute maximum ratings* temperature under bias ...................... ?65 c to +135c storage temperature ........................... ?6 5c to +150c voltage on any pin with respect to v ss ...................................... ?1v to +7v d.c. output current ............................... ................... 5ma lead temperature (soldering, 10 seconds) ................................. 300c *comment stresses above those listed under ?absolute ma ximum ratings? may cause permanent damage to the d evice. this is a stress rating only and the functional ope ration of the device at these or any other conditions above those listed in the operational sections of this s pecification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliab ility. figure 11. response to reset (rst) cs sck so 0 1 1010101 0 1001100 0 0100000 1 010101 rst 7025 fm 16 lsb msb lsb msb lsb msb lsb msb byte 0 1 2 3 response to reset (default =19 28 aa 55) the iso response to reset is controlled by the rst, cs and clk pins. when rst is pulsed high, while cs is low, the device will output 32 bits of data, one bit per clock. this conforms to the iso standard for "synchronous response to reset". cs must remain low and the part must not be in a write cycle for the response to re set to occur. after initiating a nonvolatile write cycle is compl ete. if not, the iso response will not be activated. also, any attem pt to pulse the rst pin in the middle of an iso transa ction will stop the transaction with the sda pin in high imped - ance. the user will have to issue a stop co ndition and start the transaction again. if at any time during the response to reset cs goes hgih, the response to reset will be aborted and the part will ret urn to the standby state. a response to reset is not available dur- ing a nonvolatile write cycle. continued clocks after the 32 bits, will output the 32 bit sequence again, starting at byte 0. start ack ack ack ack start ack nack stop
x76f128 10 recommended operating conditions 7052 fm t05 7052 fm t06 temp min. max. commercial 0c +70c extended ?20c +85c supply voltage limits x76f128 4.5v to 5.5v x76f128 ? 2.7 2.7v to 3.6v d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) 7052 fm t07 capacitance t a = +25c, f = 1mhz, v cc = 5v 7052 fm t08 n otes: (1) must perform a stop command after a read command pr ior to measurement (2) v il min. and v ih max. are for reference only and are not tested. (3) this parameter is periodically sampled and not 100% tested. symbol parameter limits units test conditio ns min. max. i cc1 v cc supply current (read) 1 ma f scl = v cc x 0.1/v cc x 0.9 levels @ 400 khz, sda = open rst = cs = v ss i cc2 (3) v cc supply current (write) 3 ma f scl = v cc x 0.1/v cc x 0.9 levels @ 400 khz, sda = open rst = cs = v ss i sb1 (1) v cc supply current (standby) 50 a v il = v cc x 0.1, v ih = v cc x 0.9 f scl = 400 khz, f sda = 400 khz i sb2 (1) v cc supply current (standby) 1 a v sda = v scc = v cc other = gnd or v cc ?0.3v i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc v il1 (2) input low voltage ?0.5 v cc x 0.3 v v cc = 5.5v v ih1 (2) input high voltage v cc x 0.7v cc + 0.5 v v cc = 5.5v v il2 (2) input low voltage ?0.5 v cc x 0.1 v v cc = 3.0v v ih2 (2) input high voltage v cc x 0.9v cc + 0.5 v v cc = 3.0v v ol output low voltage 0.4 v i ol = 3ma symbol test max. units conditions c out (3) output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (rst, scl, cs) 6 pf v in = 0v equivalent a.c. load circuit a.c. test conditions 7052 fm t09 3v 1.3k output 100pf 5v 1533 output 100pf 7052 fm 17 input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 output load 100pf
x76f128 11 ac characteristics ac specifications (over the recommended operating conditions) notes: 1. typical values are for t a = 25?c and v cc = 5.0v notes: 2. c b = total capacitance of one bus line in pf. symbol parameter min typ (1) max units f scl scl clock frequency, x76f128 0 400 khz f scl sch clock frequency, x76f128?2.7 0 250 khz t in (1) pulse width of spikes which must be suppressed by the input filter 50 100 ns t aa scl low to sda data out valid 0.1 0.3 0.9 s t buf time the bus must be free before a new transmit can start 1.3 s t low clock low time 1.3 s t high clock high time 0.6 s t su:sta start condition setup time 0.6 s t hd:sta start condition hold time 0.6 s t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.6 s t dh data output hold time 50 300 ns t r sda and scl rise time 20 + 0.1 x c b (2) 300 ns t f sda and scl fall time 20 + 0.1 x c b (2) 300 ns t su:cs cs setup time 200 ns t hd:cs cs hold time 100 ns f s cl_rst scl clock frequency during response to reset 400 khz t sr device select to rst active 200 ns t nol rst to scl non-overlap 500 ns t rst rst high time 2.25 s t su:rst response to reset setup time 1.25 s t low_rst clock low during response to reset 1.25 s t high_rst clock high during response to reset 1.25 s t rdv rst low to sda valid during response to reset 0 500 ns t cdv clk low to sda valid during response to reset 0 500 ns t dhz device deselect to sda high impedance 0 500 ns 7052 fm t14
x76f128 12 reset ac specifications power up timing notes: 1. delays are measured from the time v cc is stable until the specified operation can be initiat ed. these parameters are periodically sampled and no t 100% tested. 2. typical values are for t a = 25?c and v cc = 5.0v nonvolatile write cycle timing notes: 1. t wc is the time from a valid stop condition at the end of a write sequence to the end of the self-timed intern al nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. timing diagrams bus timing write cycle timing symbol parameter min. typ (2) max. units t pur (1) time from power up to read 1 ms t puw (1) time from power up to write 5 ms symbol parameter min. typ .(1) max. units t wc (1) write cycle time 5 10 ms t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r 7052 fm 18 scl sda t wc 8th bit of last byte ack stop condition start condition 7052 fm 19 7052 fm t11 7052 fm t12
x76f128 13 cs timing diagram (selecting/deselecting the part) rst timing diagram ? response to a synchronous reset guidelines for calculating typical values of bus pull up resi stors t su:cs t hd:cs scl cs from master 7052 fm 20 t rst t nol t high_rst t low_rst t cdv t rdv t su:rst data bit (1) data bit (2) 1st clk pulse 2nd clk pulse 3rd clk pulse cs i/o clk rst t nol t sr data bit (n) data bit (n+1) cs i/o clk rst t dhz (n+2) 7052 fm 21 100 80 60 40 20 bus capacitance in pf r min r max 20 40 60 80 100 r min v ccmax i olmin -------------------------- 1.8 k = = r max t r c bus ---------------- - = t r = maximum allowable sda rise time 7052 fm 22 pull up resistance in k
x76f128 14 packaging information a2 a1 l l1 gage plane 0.25 c 70 7052 fm 23 he d e b hd e notes: 1. gage plane dimension is in mm. 2. lead coplanarity shall be 0.10mm [0.004] maximum . 48 - lead thin quad flat pack (tqfp) package type l pin 1 dim inches millimeters min max min max a 1 a 2 b c d e e hd he l l 1 0.05 1.35 0.17 0.090 7.0 bsc 9.0 bsc 0.45 0.15 1.45 0.27 0.200 0.75 0.002 0.53 0.007 0.004 0.018 0.006 0.057 0.011 0.008 0.030 1.00 typ 0.039 typ 0.5 bsc 0.02 bsc 3. mold flash not included in dimensions 9.0 bsc 0.35 bsc 0.35 bsc 7.0 bsc 0.273 bsc 0.273 bsc
x76f128 15 8 pad chip on board smart card module type x 0.465 0.002 (11.81 0.05) a section a-a a r. 0.078 (2.00) 0.285 (7.24) max. see note 7 sht. 2 0.420 0.002 (10.67 0.05) 0.210 0.002 (5.33 0.05) 0.105 0.002 (2.67 0.05) typ. (8x) (8x) 0.105 0.002 (2.67 0.05) 0.008 0.001 (0.20 0.03) 0.233 0.002 (5.92 0.05) 0.174 0.002 (4.42 0.05) 0.146 0.002 (3.71 0.05) die 0.0235 (0.60) max. 0.015 (0.38) max. 0.008 (0.20) max. glob size fr4 tape see detail sheet 3 copper, nickel plated, gold flash r. 0.013 (0.33) (8x) 0.270 (6.86) max. see note 7 sht. 2 0.069 (1.75) min epoxy free area (typ.) 0.088 (2.24) min epoxy free area (typ.) note: 1. all dimensions in inches and (millimeters) sc type x ill 1.0 vcc rst scl nc vss cs sda nc
x76f128 16 ordering information v cc limits blank = 5v 10% 2.7 = 2.7v to 3.6v temperature range blank = commercial = 0c to +70c e = extended = ?20c to +85c package l = 48-lead tqfp h = die in waffle packs w = die in wafer form x = smart card module device x76f128 limited warranty devices sold by xicor, inc. are covered by the warranty and p atent indemnification provisions appearing in its terms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the info rmation set forth herein or regarding the freedom of the described devices from patent infringement. xicor, i nc. makes no warranty of merchantability or fitness for any purpose . xicor, inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any cir cuitry other than circuitry embodied in a xicor, inc. pro duct. no other circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,4 04,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,8 46; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,8 29, 482; 4,874, 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may en danger life, system designers using this product should de sign the system with appropriate error detec- tion and correction, redundancy and back-up features to prevent such an occurence. xicor?s products are not authorized for use in critical com ponents in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructio ns for use provided in the labeling, can be reasonably ex pected to result in a significant injury to the user. 2. a critical component is any component of a life support d evice or system whose failure to perform can be reasonably e xpected to cause the failure of the life sup- port device or system, or to affect its safety or effectiveness. x x x - x g = rohs complaint lead - free package blank = standard package. non lead-free

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